WP1 – QPU Critical Path

Forschungszentrum Jülich – PGI-13

• Development of a demonstrator chip
  Design a superconducting quantum processor with at least 30 individually controllable and readable qubits in a scalable architecture
  Establish calibration
• Scalable architectures
  Develop details of the keystone double chain architecture
• Gate and calibration development
  Benchmark methods for single-qubit gates and high-fidelity interleaved two-qubit gates
• Implement benchmarking and validation algorithms
  Quantify performance with trusted tools
• Coherent materials
  Improve current (Al) and develop new (nitrides, 2DEGs) materials for highly coherent quantum devices

WP2 – QPUs: Element Evolution

• Qubit control on the Bloch sphere
  Achieve 97% fidelity in state preparation and general control
  Improve parametric standing wave amplifiers
• Quasiparticle suppression and mitigation
  Develop a kinetic model and validate it experimentally
  Develop suppression of quasiparticle sources (IR, ionising radiation, etc.) by traps
• Dielectric masks, new materials and surface treatments against dielectric
  Develop dielectric template masks to improve material growth and treatment
  Validation: local scanning and coherence

WP3 – Scaling Technology

• Manufacturing processes
  Adaptation and optimisation of manufacturing processes at different scale and integration levels, characterisation and quality assurance
• Integration technology
  Research and implementation of integration and interconnection technology, including bonding, flip chip, and monolithic integration
• Base cells
  Design, fabrication and test of basic cells to demonstrate functionality
  Parameter evaluation with the developed tools
• Scalability of quantum processors
  Scaling the number of controllable qubits, implementation of adapted integration and interconnection technologies
• Control and readout components
  Research, fabrication and characterisation of components: Microwave amplifiers, e.g. TWPA and SFQ/AQFP systems
• Foundry Service
  Formulation of design rules, process description, parameters, cell library and quality management

WP4 – QPU Environment

• Cryogenic electromagnetic environment
  Simulation of the QPU electromagnetic environment for cryogenic packaging and dense, flexible radio frequency wiring for processor demonstrator and TWPAs
• TWPA for high performance
  Design/manufacture/characterisation of a nitride-based TWPA for high electrical power
• High density flexible flat wiring
  Design and fabrication of highly scalable, flat, flexible high frequency wiring and validation on demonstrator

WP5 – Hardware Integration Technology

• Cost-effective room temperature (RT) electronics
  Design/implementation/maintenance of RT electronics based on demonstrator requirements
• Optimised cryoelectronics
  Cryogenic characterisation and optimisation of GF 22FDX technology in terms of power exception/high frequency/noise performance
• Cryogenic packaging
  Development of packaging for high density electrical interconnects and thermal management/isolation for co-integration of cryogenic control with qubits
• Demonstration of cryogenic control
  Validation that QPUs can be operated with cryogenic control

WP6 – Hardware Modelling & Theory

• Modelling and suppression of noise sources for solid state qubits
  Characterise/model the complex environments that cause decoherence
  Use understanding to design methods of decoherence avoidance and stabilisation
• Modelling of multi-qubit modules
  Simulate dynamics incorporating the physics of superconductivity (Josephson effect, quasiparticle dynamics) and the full electromagnetic model of the whole system
  Adaptation of the chip design automation toolbox "KQCircuits" to the new demonstrators
• Validation and benchmarking to validate fidelities
  Development and application of test protocols to prove demonstrator fidelity and computational advantage for all platforms including Moonshot
  Application within the Qruise software package C3
• Roadmap to scalability
  Design of architectures of larger systems with fault correction and tolerance
  Use of ML-assisted quantum error correction and suppression for new processors

WP7 – Hardware Stack for External Access

Forschungszentrum Jülich – PGI-13

• Establish external access to powerful experimental infrastructure
  Explore hardware stack that allows external access to quantum processors, in particular a dedicated cryostat connected to computer-controlled control electronics
• Installation and calibration of quantum processors
  Use superconducting qubit systems as a platform for quantum algorithms
• Maintaining performance through hardware
  Minimising drift through hardware and environmental measures (noise, electronics, temperature fluctuations; software focus)

WP8 – Middle and Firmware Stack Control

Forschungszentrum Jülich – PGI-8

• Instrument control
  Quantitative simulation of the entire QPU
  Interface to experimental hardware and firmware
  Creation of a circuit programmable interface
• Gater design
  Simple few-qubit pulses with AI-assisted design tool
  Dynamically decoupled gates
  Feedback on design process
• Calibration and system identification
  Known and AI-assisted calibration
  ML methods for experimental data analysis
  Parameter reconstruction and error budget
• Measurement
  Optimisation of measurement protocols
  Improved measurement elements
  Protocols for benchmarking of gates/algorithms (randomised, gate topography) and higher metrics (quantum volume, creutentropy benchmarking)
• Scalability
  Modularity of design and characterisation to speed up calibration
• Durable operation
  Periodic recalibration of control, scheduling of calibration processes in the middle of the software stack

WP9 – Benchmark & Co-Design

• Classification of applications
  Establish a class of tasks in different scientific fields (e.g. biology or particles) and industrial problems that can be efficiently mapped to a quasi-1D geometry and potentially benefit from resonators
• Cross-platform benchmarking
  Efficient simulation of task classes implemented on simulation infrastructure and suitable QC hardware
  Application benchmarking also relative to other QC hardware
• Decoherence constraints for 1D architecture
  Establish maximum decoherence still allowing quantum advantage through simulation methods
• Better algorithms through better couplers
  Develop algorithms for advanced couplers
  Evaluation of algorithms on the double stranded geometry of the demonstrator

WP10 – HPC Integration

• Compiler
  Delivery of software that accepts quantum algorithms and determines the most efficient implementation
• Interface in the QSolid software stack
  Establish an interface between ParityOS (tasks in gate sequences) and Qruise (fast qubit calibration)
• Cloud access
  Offer interfaces for sending in programs
  Infrastructure verification and resources for end users
• HPC integration and infrastructure
  Integration for system management, usage access, health check for sustained operation and availability in a modular supercomputer
• Backend development
  Provision of common frameworks and interfaces from front-end to QPU
• Scheduling and resource management
  Efficient provision of quantum hardware between many users as part of heterogeneous workflows
• Coordination of software development
  Coordinate software architecture and development activities between partners
  Continuous integration and validation

WP11 – Technical & Global Management

• Management/communication structures
  Establishment of an internal management platform and workflows
• Continuous monitoring and planning
  Regular exchange between work packages
• Meetings and onboarding
  Organise annual consortium meetings (two face-to-face days), onboarding workshops and inter-WP meetings
• External communication, networking, stakeholder engagement, contract management
  Support consortium-wide reporting and coordination, liaise with other projects, liaise with funders and the public
• Integration management
  Top-down system engineering – detailed development and monitoring of interface specifications, requirements, specifications, integration and test plan, interface verification and assessment of systemic risks
• Outreach and communication
  CI, communication material, media presence, project website, audio-visual material
• Coordination of exploitation
  Information material for exploitation centres, training for staff, query and coordination of joint exploitation